Many years of research have been devoted to reducing the critical dimensions (CDs) and structure densities of integrated circuits (ICs). As densities have increased, the resistance capacitance (RC) delay time has become a limiting factor in circuit performance. To reduce the RC delay, there has been a desire to replace the dielectrics in damascene metal interconnect structures with materials having lower dielectric constants. Such materials are referred to as low-k and extremely low-k dielectrics. A low-k dielectric is a material having a smaller dielectric constant than SiO2. SiO2 has a dielectric constant of about 4.0. An extremely low-k dielectric is a material having a dielectric constant of about 2.1 or less.
The theoretical advantages of using extremely low-k dielectrics in damascene metal interconnect structures have been offset by the practical difficulty of integrating these materials into manufacturing processes. Extremely low-k dielectrics typically have large pores and high overall porosity. These properties make the extremely low-k dielectric layers susceptible to intrusion and damage during high energy plasma etching, particularly when the etch gas includes oxygen. Etch damage can reduce device reliability and offset the gains in RC performance achieved by switching from low-k to extremely low-k dielectrics. There has been a long felt need for a process that economically incorporates extremely low-k dielectrics into semiconductor devices in a way that produces reliable devices with reduced RC delay.